More testing of the memory and I/O address decoder PLD

I have been testing the current breadboard circuit.  I decided to add in an 82C51A UART with the intention of writing some code just to test the Z88DK software development suite, which I finally got to compile properly.  More on that in another post.

As stated in the last post, I had a few I/O pins left on the AFT16V8B and thought I could use them to remove some of the individual 74HC04 inverters by incorporating the functions into the PLD.   In looking at the signals from the address decoder PLD, namely the Z80 Clock, I noticed that the output of the PLD was only about 3.25 volts peak, which is a bit low to be driving the clock inputs of 5 volt logic input.  I ended up removing the clock buffering from the PLD.  I may use a single pico-gate for the clock buffer.

The updated CUPL code is below.

Next up, getting the Z88DK software development suite up and running.

Name Z80_IOdecode-1V10;
PartNo Z80C;
Date 10/18/2016;
Revision 01;
Designer Quest, Johnny;
Company JQ;
Assembly Z80 Computer;
Location U4;
Device g16v8a;

/***** Z80 Address Decoder ******************************
 *           ______________
 *          | Z80_IOdecode |
 *      x---|1 I         20|---x Vcc
 * mreq x---|2 I       O 19|---x RST_H
 * iorq x---|3 I       O 18|---x 
 *  a10 x---|4 I       O 17|---x !IO1_cs
 *  a11 x---|5 I       O 16|---x !IO0_cs
 *  a12 x---|6 I       O 15|---x !RAM1_cs
 *  a13 x---|7 I       O 14|---x !RAM2_cs
 *  a14 x---|8 I       O 13|---x !PIO_cs
 *  a15 x---|9 I       O 12|---x !AVR_cs
 *  GND x---|10 I      I 11|---x rst_l 
 *          |______________|
 */
/********************************************************/
/* This device generates chip select signals for two */
/* 32Kx8 static RAMs, the 82C55A PIO and the AVR's INT0 */
/* line. */
/********************************************************/

/** Inputs **/
PIN 2 = mreq; /* Z80 MREQ (active low) */
PIN 3 = iorq; /* Z80 IORQ (active low) */
PIN [4..9] = [a10..a15]; /* upper 6 address bits */
PIN 11 = rst_l; /* AVR Z80 RESET (active low) */

/** Outputs **/
PIN 18 = RST_H; /* SYS RST (active high) */
PIN 17 = IO0_cs; /* Auxiliary I/O Select 0 (active low) */
PIN 16 = IO1_cs; /* Auxiliary I/O Select 1 (active low) */ 
PIN 15 = RAM1_cs; /* 32Kx8 RAM (active low) */
PIN 14 = RAM2_cs; /* 32Kx8 RAM (active low) */
PIN 13 = PIO_cs; /* 82C55A PIO (active low) */
PIN 12 = AVR_cs; /* SDmemory interface (active low) */

/** Declarations and Intermediate Variable Definitions **/
FIELD address = [a15..10]; /* upper 6 addresses */

avr_eqn = !iorq & address:[0000..03FF]; /*******************************/
pio_eqn = !iorq & address:[0400..07FF]; /* */
io0_eqn = !iorq & address:[0800..0BFF]; /* I/O Address */
io1_eqn = !iorq & address:[0C00..0FFF]; /* Ranges */
 /* */
ram1_eqn = !mreq & address:[0000..7FFF]; /* */
ram2_eqn = !mreq & address:[8000..FFFF]; /*******************************/

/** Logic Equations **/
RST_H = !rst_l; /* Needed for INTEL peripherals */

AVR_cs = !avr_eqn; /* AVR - low for addresses 0000h-03FFh */
PIO_cs = !pio_eqn; /* PIO - low for addresses 0400h-07FFh */

IO0_cs = !io0_eqn; /* IOO - low for addresses 0800h-0AFFh */
IO1_cs = !io1_eqn; /* IO1 - low for addresses 0B00h-0FFFh */

/* RAM select (active low) */
RAM1_cs = !ram1_eqn; /* low for RAM addresses 0000h-7FFFh */
RAM2_cs = !ram2_eqn; /* low for RAM addresses 8000h-FFFFh */
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