Project goals as thoughts and concepts now put into words …

I have all these thoughts and concepts of how I would like to materialize this project into the final goals stored in my mind on “virtual paper”, if you will.  As with most projects, as the project continues, my thoughts and ideas are also evolving.  Thus, I thought it was time to put those thoughts onto “real paper”.  What follows is the culmination of those thoughts.  Keeping in mind, off course, that there may be future additions, deletions and modifications to it.

Summary: A Z80-based single board computer with 64KB of RAM and 24 bits of I/O, capable of running CP/M and other programs, including BASIC and FORTH, with some program debugging aids.

Features: The Z80 SBC uses an AVR (AT90usb1286) as a “host controller” or “System Supervisor”. The AVR has complete control of the Z80 system buses, allowing it to fully interact with the Z80’s memory and PIO controller. Using the Z80 BUSREQ signal, the AVR can write to and read from the Z80 memory, including transferring program/data images to and from a micro-SD memory card.

Upon a power-up or hardware reset, the AVR holds the Z80 CPU in a reset condition so it can read a “boot sector” (and/or other binary images) from a file on the SDmem card, which is loaded into the Z80 memory at address 0x0000 (and/or other addresses).  Once the RESET line is released, the Z80 is then allowed to execute the code from memory address 0x0000.

In normal use, the AVR will act as a serial-I/O device between the user’s console and the Z80 by emulating an 82C51A UART (or the like) for the Z80. While the AVR is emulating the UART, it will monitor the user’s input for a “Data Link Escape” (DLE) character (a.k.a. CTRL-P), at which time it will enter into a “monitor” program to allow the user to configure features of the Z80 SBC and other functions as yet to be determined.

The AVR will emulate for the Z80, several hardware peripheral devices. At 16 MHz, the AVR does not run fast enough to be able to assert the Z80 WAIT signal within the 875 nS required, thus a key component in the AVR host controller scheme is a separate wait-state generator implemented in a GAL22V10D PLD. The wait-state generator is partly controlled by the AVR in that the AVR determines how many wait-states are required at the selected Z80 clock speed and manipulates an internal MUX within the GAL22V10D using two (2) control lines (S0 and S1).  The wait-state generator handles the initial WAIT signal assertion giving the AVR time to respond and continue the WAIT signal assertion until it can complete the expected task.

The hardware devices emulated are as follows:

  • Intel 82C51A (or Z80SIO) UART

  • Intel 8272 (a.k.a. uPD765A) Floppy Disk Controller

  • (possibly) Intel 8237 DMA controller

  • MAXIM DS3231 (or DS1307 or equivalent) Real-Time Clock

  • Single-step function for simplistic (or possibly more advanced) code debugging

The AVR will respond to a Z80 address decoded as it’s “chip-select”, which will act as a hardware interrupt to the AVR. The wait-state generator will assert the Z80’s WAIT signal long enough for the AVR to respond by continuing the assertion of the Z80 WAIT signal. The AVR will decode the lower 8 address bits to determine which of the four (4) emulated peripheral devices it will emulate the function(s) of and respond as.

Emulated Peripherals:

  1. 82C51A – a simple UART with control/status and data read/write registers. Many CP/M BIOS implementations already support the 82C51A as a UART peripheral.  An MC68B50 could also be emulated as an alternative, perhaps allowing a selection between both as a configuration option.

  2. 8272 (or uPD765A) – a floppy disk controller that responds to read and write requests as a floppy disk drive interface. Only a subset of the 8272 commands are required. In practice, it would be best to directly transfer the data to/from the SDmem card and the Z80’s memory buffer rather than use an emulated DMA or respond to single-byte transfer between the Z80 and the emulated 8272.  The 8272/uPD765 was a commonly supported peripheral by Z80 and S-100 computers of that era, so the CP/M BIOS supports it. 

  3. 8237 – Direct Memory Access (DMA) controller. Likely not needed but if the CP/M BIOS needs it to function with disk-to-memory transfers then emulation should be fairly simple to implement.

  4. DS3231 – Real-time Clock and calendar. The AVR will use a software library to interface with the FAT file system on an SDmem card. The FAT FS library optionally supports time and date stamping of files, thus a hardware-based RTC will be connected to the AVR via its I2C bus. Since the hardware RTC already exists, emulating a hardware RTC for the Z80 should be easy to implement. Although, it may not be needed.

  5. Single-stepping – a popular feature on computers of the Z80 era. It is simple to implement a single-stepping feature using the AVR. Debugging code on the Z80 will be no trivial task as there is no way to access the Z80’s internal registers as was done in the days of the Z80 using a hardware emulator. However, the Z80’s clock will be under control of the AVR, which will range from 8 MHz down to 31.25 KHz. With the slowest Z80 clock speed of 31.25 KHz, the AVR can monitor the Z80’s address, data and control buses with ease. In theory, “shadow registers” can be emulated in AVR memory.  Software emulators have been doing this for years.  In operation, each and every opcode and operand can be decoded and the AVR could in fact, keep track of and update all “shadow registers” of the Z80.  This feature would be extremely helpful in debugging Z80 code on actual the hardware as folks have complained that many of the current Z80 simulators do not properly emulate some hardware devices. It is however, a huge undertaking BUT there is a Z80 emulator that has been coded for the AVR, which may make this feature much easier to implement.  More research is needed on the potential imple-mentation of this feature and the use of a software Z80 emulator.

Specific AVR software functional blocks:

  1. Console I/O with the user via the AVR’s USB CDC device emulation.

  2. Setting of Z80 system clock frequency.

  3. Write to and read from the Z80 memory.

  4. Write to and read from an SD memory card using the FAT FS library.

  5. Write to and read from a DS3231 (or DS1307) RTC.

  6. Emulate the 82C51A (or MC68B50) UART.

  7. Emulate the 8272 floppy-disk controller.

  8. Single-stepping – basic implementation.

  9. Single-stepping – with complete Z80 register emulation.

  10. Z80 memory test.

  11. Direct manipulation of 82C55A I/O pins.

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